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authorKyle Isom <kyle@tyrfingr.is>2014-01-29 10:19:30 -0700
committerKyle Isom <kyle@tyrfingr.is>2014-01-29 10:19:30 -0700
commit6bd13035db4c61bf09b993dff932a58e7afcf900 (patch)
treefb447adcfe073cbd336c98a79092c04791b54240
parent11fa1537116befdf70412acb8b4ac0c9b354676c (diff)
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Most of the addressing is now handled.
-rw-r--r--src/cpu.cc51
-rw-r--r--src/cpu.h29
2 files changed, 59 insertions, 21 deletions
diff --git a/src/cpu.cc b/src/cpu.cc
index e86e74c..c4a665d 100644
--- a/src/cpu.cc
+++ b/src/cpu.cc
@@ -628,10 +628,32 @@ CPU::step()
op = this->ram.peek(this->pc);
this->step_pc();
- if (op == 0x00) {
- std::cerr << "[DEBUG] OP: BRK\n";
+ // Scan single-byte opcodes first
+ switch (op) {
+ case 0x00: // BRK
this->BRK();
return false;
+ case 0x10: // BPL
+ this->BPL(this->read_immed());
+ return true;
+ case 0x30: // BMI
+ this->BMI(this->read_immed());
+ return true;
+ case 0x50: // BVC
+ this->BVC(this->read_immed());
+ return true;
+ case 0x70: // BVS
+ this->BVS(this->read_immed());
+ return true;
+ case 0x90: // BCC
+ this->BCC(this->read_immed());
+ return true;
+ case 0xB0: // BCC
+ this->BCS(this->read_immed());
+ return true;
+ case 0xD0: // BNE
+ this->BNE(this->read_immed());
+ return true;
}
switch (op & cc) {
@@ -645,12 +667,9 @@ CPU::step()
this->instrc10(op);
return true;
default:
- switch (op) {
- default:
- std::cerr << "[DEBUG] ILLEGAL INSTRUCTION (cc): "
- << std::setw(2) << std::hex << std::setfill('0')
- << (unsigned int)(op&0xff) << std::endl;
- }
+ std::cerr << "[DEBUG] ILLEGAL INSTRUCTION (cc): "
+ << std::setw(2) << std::hex << std::setfill('0')
+ << (unsigned int)(op&0xff) << std::endl;
}
return false;
}
@@ -787,6 +806,11 @@ CPU::read_addr1(uint8_t mode)
addr = this->read_immed();
addr += ((uint16_t)this->read_immed() << 8);
break;
+ case C01_MODE_IIZPY:
+ addr = this->read_immed();
+ addr = this->ram.peek(addr) + (this->ram.peek(addr+1)<<8);
+ addr += this->y;
+ break;
case C01_MODE_ZPX:
addr = (uint8_t)(this->read_immed() + this->x);
break;
@@ -826,6 +850,17 @@ CPU::read_addr2(uint8_t mode)
addr = this->read_immed();
addr += ((uint16_t)this->read_immed() << 8);
break;
+ case C10_MODE_X:
+ addr = (uint8_t)(this->read_immed() + this->x);
+ break;
+ case C10_MODE_Y:
+ addr = (uint8_t)(this->read_immed() + this->y);
+ break;
+ case C10_MODE_ABS_X:
+ addr = this->read_immed();
+ addr += ((uint16_t)this->read_immed() << 8);
+ addr += this->x;
+ break;
default:
debug("INVALID ADDRESSING MODE");
addr = 0;
diff --git a/src/cpu.h b/src/cpu.h
index 4913d37..b58ba3f 100644
--- a/src/cpu.h
+++ b/src/cpu.h
@@ -51,6 +51,7 @@ class CPU {
cpu_register16 pc;
RAM ram;
+ // CPU control
void reset_registers(void);
void instrc01(uint8_t);
void instrc10(uint8_t);
@@ -59,23 +60,10 @@ class CPU {
uint16_t read_addr0(uint8_t); // cc = 00
uint16_t read_addr1(uint8_t); // cc = 01
uint16_t read_addr2(uint8_t); // cc = 10
- bool step(void);
- public:
- CPU();
- CPU(size_t);
-
- void dump_registers(void);
- void dump_memory(void);
- void run(bool);
-
- // Memory access
- void load(const void *, uint16_t, uint16_t);
- void store(void *, uint16_t, uint16_t);
// PC instructions
void step_pc(void);
void step_pc(uint8_t);
- void start_pc(uint16_t);
// status register
void BRK(void);
@@ -114,6 +102,21 @@ class CPU {
void BCS(uint8_t);
void BNE(uint8_t);
void BEQ(uint8_t);
+ public:
+ CPU();
+ CPU(size_t);
+
+ void dump_registers(void);
+ void dump_memory(void);
+ void run(bool);
+ bool step(void);
+ void start_pc(uint16_t);
+
+ // Memory access; use this to load a memory image or
+ // write a memory image out.
+ void load(const void *, uint16_t, uint16_t);
+ void store(void *, uint16_t, uint16_t);
+
};